Field of the Invention
The present invention relates to a test system and a device forming the test system.
Description of the Related Art
In conventional integrated circuit (IC) fabrication, many discrete ICs are formed as chips (dice) on the surface of a semiconductor wafer. After the fabrication process is complete, the wafer is scribed, thereby dividing the wafer into the individual chips. Each chip is then packaged into modules or incorporated into larger systems.
Due to defects in the wafer, or defects in one or more of the processing steps of the fabrication process, some of the individual chips may not function as designed. These defects may show up initially or may not be apparent until the chip has been in operation for an extended period of time. In order to identify the latent defective chips, a burn-in procedure is performed on the chips. During the burn-in procedure, the chips are hastened at the elevated temperature and a test controller statically or dynamically applies a set of bias voltages to selected chips so as to cause current conduction in the selected chips. After the burn-in procedure is complete, the chips undergo a chip probe (CP) test to screen out the latent defective chips prior to packaging.
During the traditional wafer level burn-in procedure, the chips only receive the set of bias voltages and will not sent back signals to the test controller. Therefore, the controller cannot confirm whether the burn-in procedure is certainly performed. For example, there may be a short or an open condition in the path between the controller and the chips, preventing the bias voltages from transmitting to the chips. As a result, the burn-in cannot be performed on the chips and the controller will mistake the non-burned chips for the latent defect chips during the following CP test.